NEC PD78058FY(A) podręczniki

Nec PD78058FY(A) Instrukcja Użytkownika (593 strony)

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Spis treści

PD78058F, 78058FY Subseries

1

NOTES FOR CMOS DEVICES

3

M7 96.5

4

Regional Information

5

bus interface) mode √ —

10

mode — √

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Other Documents

13

LIST OF FIGURES (1/8)

23

LIST OF FIGURES (2/8)

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LIST OF FIGURES (3/8)

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LIST OF FIGURES (4/8)

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LIST OF FIGURES (5/8)

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LIST OF FIGURES (6/8)

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LIST OF FIGURES (7/8)

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LIST OF FIGURES (8/8)

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LIST OF TABLES (1/3)

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LIST OF TABLES (2/3)

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LIST OF TABLES (3/3)

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CHAPTER 1 OUTLINE (

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1.1 Features

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1.2 Applications

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1.3 Ordering Information

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1.4 Quality Grade

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CHAPTER 1 OUTLINE (

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12 mm)

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Pin Identifications

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1.6 78K/0 Series Expansion

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10-bit timer: 1 channel

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2. 10-bit timer: 1 channel

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1.7 Block Diagram

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1.8 Outline of Function

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1.9 Differences Between the

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PD78058F and

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PD78058F(A)

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1.10 Mask Options

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CHAPTER 2 OUTLINE (

47

2.1 Features

47

2.2 Applications

48

2.3 Ordering Information

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2.4 Quality Grade

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CHAPTER 2 OUTLINE (

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2.6 78K/0 Series Expansion

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2.7 Block Diagram

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2.8 Outline of Function

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2.9 Differences Between the

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PD78058FY and

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PD78058FY(A)

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2.10 Mask Options

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CHAPTER 3 PIN FUNCTION (

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3.1 Pin Function List

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(1) Port pins (2/3)

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(2) Non-port pins (1/2)

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DD — Positive power supply

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SS — Ground potential

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CHAPTER 3 PIN FUNCTION (

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As short as possible

72

CHAPTER 4 PIN FUNCTION (

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4.1 Pin Function List

77

CHAPTER 4 PIN FUNCTION (

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CHAPTER 5 CPU ARCHITECTURE

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5.1 Memory Spaces

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Figure 5-2. Memory Map (

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PD78058F, 78058FY)

101

PD78P058F, 78P058FY)

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5.2 Processor Registers

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CHAPTER 5 CPU ARCHITECTURE

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Register Register

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(b) Function Name

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(a) Absolute Name

107

Identifier Description

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01010000 50H (immediate data)

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[Illustration]

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— [DE], [HL]

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— [HL + byte]

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— [HL + B], [HL + C]

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CHAPTER 6 PORT FUNCTIONS

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6.1 Port Functions

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Table 6-1. Port Functions (

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PD78058F Subseries) (1/2)

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Table 6-2. Port Functions (

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PD78058FY Subseries) (1/2)

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6.2 Port Configuration

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CHAPTER 6 PORT FUNCTIONS

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P00/INTP0/TI00

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Internal bus

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PM : Port mode register

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RD : Port 2 read signal

136

WR : Port 2 write signal

136

RD : Port 7 read signal

143

WR : Port 7 write signal

143

P10 to P17

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Input/Output

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ANO0, ANO1 Output 1 ×

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6.4 Port Function Operations

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6.5 Selection of Mask Option

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CHAPTER 7 CLOCK GENERATOR

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Selector

156

Feedback resistor

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CHAPTER 7 CLOCK GENERATOR

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X = 5.0 MHz, fXT = 32.768 kHz

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Remarks f

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7.4 System Clock Oscillator

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X2 ICX1 X2 ICX1

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(n = 0 to 7, 12, 13)

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X = 5.0 MHz and f

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XT = 32.768 kHz

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X) is secured automatically

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8.1 Overview of the

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Watch Timer Watchdog Timer

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X = 5.0 MHz

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Inversion operation disabled

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Inversion operation enabled

183

CRC00CRC01CRC02

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CRC0 00/10/100000

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CR00 set as compare register

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AN = VREF ×

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≤ CR01 < CR00 ≤ FFFFH

192

CRC0 00/1100000

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CR01 set as capture register

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CRC0 10100000

195

CR00 set as capture register

195

OVF0TMC01TMC02TMC03

200

TMC0 00/1110000

202

TMC0 00110000

204

Timer Start

208

Count Pulse

208

2, respectively

217

SCK : Serial clock frequency

218

TM1, TM2 Count Value

236

00H 01H 02H 03H 04H

236

CR10, CR20

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X-1 X FFH 00H 01H 02H

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CHAPTER 10 WATCH TIMER

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10.1 Watch Timer Functions

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CHAPTER 10 WATCH TIMER

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10.4 Watch Timer Operations

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CHAPTER 11 WATCHDOG TIMER

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CHAPTER 11 WATCHDOG TIMER

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PCL/P35 Pin Output

253

CHAPTER 14 A/D CONVERTER

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14.1 A/D Converter Functions

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CHAPTER 14 A/D CONVERTER

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14.5 A/D Converter Cautions

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CHAPTER 15 D/A CONVERTER

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15.1 D/A Converter Functions

279

CHAPTER 15 D/A CONVERTER

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PD78058F, 78058FY

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PD78058F SUBSERIES)

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RESET input sets SBIC to 00H

302

SO0 latch

303

"H"

308

SB0 (SB1)

308

D7 D6 D5 D4 D3 D2 D1 D0

310

12345678

310

(4) Various signals

317

Figure 16-22. ACKT Operation

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Figure 16-25. BSYE Operation

320

ACK BUSY

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Note 2 Note 2

332

SO0 Latch

335

PD78058FY SUBSERIES)

337

Note 2

350

SDA0(SDA1)

365

(b) Data

375

(c) Stop Condition

376

Wait request signal

386

Timer Clock

389

Select Register 3

389

BUSY1 BUSY0

394

Shift Register 1

400

Operation

400

Interval Interval

419

D7 D6 D5

419

Interval

429

TPS3 TPS2 TPS1 TPS0

436

MDL3 MDL2 MDL1 MDL0

436

RESET input sets ASIM to 00H

447

RESET input sets BRGC to 00H

463

SCK) selected with

469

CY = 0.4

469

CY = 0.2

469

[Example]

470

PSW and PC Save, Jump

492

CPU: CPU clock)

496

1 Instruction

499

Execution

499

21.5 Test Functions

502

(a) Memory Map of the

506

Lower Address

513

CHAPTER 23 STANDBY FUNCTION

515

X, not 2

516

Oscillation

519

XT is selected as

520

X: 5.0 MHz

522

CHAPTER 24 RESET FUNCTION

523

24.1 Reset Function

523

CHAPTER 24 RESET FUNCTION

525

CHAPTER 25 ROM CORRECTION

527

25.1 ROM Correction Functions

527

Source program

530

25.5 ROM Correction Example

533

25.6 Program Execution Flow

534

CHAPTER 26

537

PD78P058F, 78P058FY

537

26.3 PROM Programming

540

G = Start address

542

N = Last address of program

542

G = Start address

544

A0 to A16

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D0 to D7

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DD and VPP pins

546

CHAPTER 27 INSTRUCTION SET

549

CHAPTER 27 INSTRUCTION SET

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27.2 Operation List

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Note 1 Note 2

554

8 + n + m

556

12 + n + m

556

(1) 8-bit instructions

560

[HL + B] $addr16

561

[HL + C]

561

78058FY Subseries

567

Hardware

569

B.2 PROM Programming Tool

571

B.3 Debugging Tool

572

B.4 OS for IBM PC

576

Based on EV-9200GC-80

577

(1) Package drawing (in mm)

577

Reference diagram: TGK-080SDW

579

Package dimension (unit: mm)

579

C.1 Real-time OS (1/2)

582

Real-time OS (2/2)

583

APPENDIX D REGISTER INDEX

585

APPENDIX D REGISTER INDEX

586

APPENDIX E REVISION HISTORY

591

Facsimile

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