NEC PD17062 Instrukcja Użytkownika Strona 171
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171
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PD17062
14. RESET
The reset function is used to initialize device operation.
14.1 RESET BLOCK CONFIGURATION
Fig. 14-1 shows the configuration of the reset block.
Device reset is divided into reset by turning on V
DD (power-on reset or VDD reset), and reset by CE pin (CE
reset).
The power-on reset block consists of a voltage detection circuit that detects the voltage applied to the VDD
pin, a power failure detection circuit, and a reset control circuit.
The CE reset block consists of a circuit that detects the rising edge of the signal input to the CE pin, and
a reset control circuit.
Fig. 14-1 Reset Block
X
OUT
X
IN
V
DD
CE
Power-on clear signal (POC)
Reset signal
IRES
RES
RESET
STOP instruction
R
S
Q
Selector
Timer carry FF
Timer FF block
Power failure detection block
Scaler
BTM0CY
flag read
STOP
instruction
Voltage
detection
circuit
Control register
System register
Stack
Program counter
Forced halt by
timer carry FF
Rising edge
detection
circuit
Timer carry
disable FF
Reset
control
circuit
- MOS INTEGRATED CIRCUIT 1
- ORDERING INFORMATION 2
- FUNCTION OVERVIEW 2
- PIN CONFIGURATION (TOP VIEW) 3
- PD17062GC-×××-3BE 4
- BLOCK DIAGRAM 5
- 1. PINS 11
- RESET signal (except for P1C) 14
- A/D Converter 15
- High on-state 15
- P0B3/HSCNT 16
- P0B2/TMIN 16
- (Hysteresis input) 17
- 2. PROGRAM MEMORY (ROM) 18
- 3. PROGRAM COUNTER (PC) 25
- 4. STACK 26
- DD is applied 28
- 5. DATA MEMORY (RAM) 29
- R, (r)) ← (m) 42
- Row address 43
- Discrimi 50
- R and mC 51
- 8. SYSTEM REGISTER (SYSREG) 54
- 2-b0, 7BH b3), of 57
- Comparison 59
- Transfer 59
- Example 1. ADD03H,11H 61
- Specifies the source 61
- 0 b3 b2 b1 b0 66
- 9. REGISTER FILE (RF) 67
- Peripheral hardware 70
- StackTimerInterrupt 70
- C bus method 72
- (only for 2-wire method) 72
- 2) (SPb0) 75
- 9.3 CE (07H, b0) 76
- NC pin and VSYNC pin 80
- 0 INTNC pin 87
- 1 Clock timer 87
- 2 VSYNC pin 87
- 3 Serial interface 87
- 10. DATA BUFFER (DBF) 88
- 0 to bit6.) 95
- Peripheral 100
- 11. INTERRUPT 106
- BANK PSW 107
- NC pin) 108
- NC pin) can be selected 108
- Serial interface 01H 109
- INTNC pin 04H 109
- Timer 03H 109
- VSYNC pin 02H 109
- NC pin), each type of 111
- NC pin) is used 114
- (a) Hardware priorities 115
- (b) Software priorities 115
- 0 of the 116
- 3 b2 b1 b0 b3 b2 b1 b0 121
- SYNC pin 121
- Active edges of interrupt 122
- SYNC pinINTNC pin 122
- System register restoration 131
- Interrupt permission 131
- 12. TIMER 133
- 2/TMIN pin 134
- 2/TMIN pin by 5 or 6 134
- CHECK < tSET 138
- SET < error < tCHECK 140
- CHECK + tTIMER < tSET 142
- Interrupt pending 149
- Input latch 153
- DD is turned on 155
- 0 at address 07H) 155
- 14. RESET 171
- Reset signal 173
- (b) At clock-stop 179
- (c) When VDD rises from 0 V 179
- During this period 182
- DD is dropped 183
- DD or by the CE pin, as 184
- DD is turned on, they 184
- Operation stopped 185
- 15. GENERAL-PURPOSE PORT 189
- 3 b2 b1 b0 191
- Note Nothing is mapped to b 193
- 3, P0A2 pins) 194
- 3, P0B2, P0B1, P0B0 pins) 194
- 3, P1B2, P1B1, P1B0 pins) 194
- 3, P1C2, P1C1 pins) 194
- 1, P0A0 pins) 194
- At reset 195
- 3, P0D2, P0D1, P0D0 pins) 198
- 3, P0C2, P0C1, P0C0 pins) 199
- 3, P1A2, P1A1, P1A0 pins) 199
- 16. SERIAL INTERFACE 201
- Remark × : Don’t care 202
- Remark ×: Don’t care 203
- 3 is used as an SO pin 205
- 1/SCL pin for 206
- Bit position b3 b2 b1 b0 207
- 6789123456789 208
- SCL, SCK 208
- Bit counter 208
- Flag name SBACK SIO0NWT 209
- SIO0WRQ1 SIO0WRQ0 209
- 17. D/A CONVERTER 217
- 6 b5 b4 b3 b2 b1 b0 218
- 3 b2 b0b1 223
- N” of the 226
- (2) When fN is leading fr 227
- (4) When fN is lower than fr 227
- Upon reset 229
- (PLLUL flag = 1) 230
- 19. A/D CONVERTER 233
- REF = VDD × 234
- DD = 5 V 234
- Flowchart 238
- 20. IMAGE DISPLAY CONTROLLER 240
- Blank (black) 241
- Background (TV screen) 241
- Sample program 244
- 01 234 5 6789AB 249
- 800001 400 249
- ID field Data field 250
- VRAM column address 250
- 7 b6 b5 b4 b3 b2 b1 b0 252
- 0 BANK0 0800H-0BFFH 255
- 1 BANK1 0C00H-0F7FH 255
- 14 and b13 of control data) 258
- 10 corresponding 259
- 10 to b7 of the control data) 259
- 6 to b3 of the control data) 260
- 6 corresponding 260
- 2 to b0 of the control data) 261
- 7 b6 b5 b4 b3 b2 b1 b0 264
- 3 b2 b1 b0 b3 b2 b1 b0 264
- IDC image area 265
- SYNC and 267
- SYNC signals supplied to the 267
- SYNC signal that comes 267
- 20.8 SAMPLE PROGRAMS 268
- 269
- 22. INSTRUCTION SETS 277
- The reserved 282
- 23.1 SYSTEM REGISTER 282
- 23.2 DATA BUFFER 282
- 23.3 PORT REGISTER 283
- 23.4 REGISTER FILES 284
- NC interrupt request flag 285
- 23.6 OTHERS 286
- 64 PIN PLASTIC QFP ( 14) 290
- SMD Surface Mount 291
- Technology Manual 291
- APPENDIX DEVELOPMENT TOOLS 292
- Cautions on CMOS Devices 295
- M4 94.11 296
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