NEC N8101-732F Arkusz Danych Strona 126
- Strona / 216
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
Intel® Xeon® Processor E5-2400 v2 Product Family 126
Datasheet Volume One
Electrical Specifications
The processor core frequency is configured during reset by using values stored within
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured via the IA32_PERF_CTL MSR (MSR 199h); Bits
[15:0]. For details of operation at core frequencies lower than the maximum rated
processor speed, refer to the
Intel® Xeon® Processor E5 v2 Product Family Datasheet,
Volume Two: Registers .
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with
exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP,
BCLK{0/1}_DN inputs are provided in Table 7-17. These specifications must be met
while also meeting the associated signal quality specifications outlined in Section 7.9.
Details regarding BCLK{0/1}_DP, BCLK{0/1}_DN driver specifications are provided in
the
CK420BQ Clock Synthesizer/Driver Specification.
7.1.6.1 PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to Table 7-12for DC
specifications and to the
Platform Design Guide (PDG) for decoupling and routing
guidelines.
7.1.7 JTAG and Test Access Port (TAP) Signals
Due to the voltage levels supported by other components in the JTAG and Test Access
Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by
any other components within the system. Please refer to the
Intel® Xeon® Processor
E5-2400 v2 Product Family – Boundary Scan Description Language (BSDL) File for
more details. A translation buffer should be used to connect to the rest of the chain
unless one of the other components is capable of accepting an input of the appropriate
voltage. Two copies of each signal may be required with each driving a different voltage
level.
7.1.8 Processor Sideband Signals
The processor include asynchronous sideband signals that provide asynchronous input,
output or I/O signals between the processor and the platform or Platform Controller
Hub. Details can be found in Table 7-5 and the applicable platform design guide.
All Processor Asynchronous Sideband input signals are required to be
asserted/deasserted for a defined number of BCLKs in order for the processor to
recognize the proper signal state. Refer to Section 7.9 for applicable signal integrity
specifications.
7.1.9 Power, Ground and Sense Signals
Processors also include various other signals including power/ground and sense points.
Details can be found in Table 7-5 and the applicable platform design guide.
7.1.9.1 Power and Ground Lands
All V
CC
, V
CCPLL,
V
SA
, V
CCD,
V
TTA
, and V
TTD
lands must be connected to their respective
processor power planes, while all V
SS
lands must be connected to the system ground
plane. Refer to the
Platform Design Guide (PDG) for decoupling, voltage plane and
routing guidelines for each power supply voltage.
- Product Family 1
- Table of Contents 3
- Datasheet Volume One 10
- Revision History 11
- 1 Overview 13
- 1.1.2 Supported Technologies 14
- 1.2 Interfaces 15
- 1.2.2 PCI Express* 16
- Transaction 17
- Overview 18
- 1.3 Power Management Support 19
- 1.5 Package Summary 20
- 1.6 Terminology 20
- 1.7 Related Documents 22
- 1.9 State of Data 23
- 2 Interfaces 24
- 2.2 PCI Express* Interface 25
- 2.2.1.1 Transaction Layer 26
- 2.2.1.2 Data Link Layer 26
- 2.2.1.3 Physical Layer 26
- 2.3.1 DMI2 Error Flow 27
- 2.3.3 DMI2 Link Down 27
- Interfaces 28
- 2.5.1.1 Thermal Management 30
- 2.5.2.1 Ping() 30
- 2.5.2.2 GetDIB() 31
- Reserved 32
- # of Domains 32
- Byte# 5 32
- 2.5.2.3 GetTemp() 33
- 2.5.2.4 RdPkgConfig() 34
- 2.5.2.5 WrPkgConfig() 35
- DRAM Power Limit Performance 45
- CPU ID Data 48
- CPU code patch revision 49
- Current Config Limit Data 54
- RESERVED 54
- Accumulated Energy Status 55
- Accumulated CPU Energy 55
- Accumulated CPU Throttle Time 57
- 2.5.2.7 RdIAMSR() 59
- Cores 0,1.2...7 60
- Thread (0,1) Mask for Core4 60
- 2.5.2.8 RdPCIConfig() 63
- 2.5.2.9 RdPCIConfigLocal() 64
- DeviceBus Function Register 65
- 2.5.2.10 WrPCIConfigLocal() 66
- 2.5.3.1 Power-up Sequencing 68
- 2.5.3.2 Device Discovery 69
- 2.5.3.3 Client Addressing 69
- 2.5.3.4 C-states 70
- 2.5.3.5 S-states 71
- 2.5.3.6 Processor Reset 71
- 2.5.4 Multi-Domain Commands 73
- 2.5.5.1 Abort FCS 74
- 2.5.5.2 Completion Codes 74
- 2.5.7.1 Format 75
- 3 Technologies 77
- 3.1.2 Intel® VT-x Features 78
- 3.1.3 Intel® VT-d Objectives 78
- 3.2 Security Technologies 79
- 3.2.3 AES Instructions 80
- 3.3 Intel® Secure Key 81
- 3.4 Intel® OS Guard 81
- Technologies 82
- 4 Power Management 85
- Table 4-6. Intel® QPI States 87
- 4.2.2 Low-Power Idle States 88
- Processor Package State 89
- Core N State 89
- Core 0 State 89
- 4.2.4.1 Core C0 State 90
- 4.2.4.2 Core C1/C1E State 90
- 4.2.4.3 Core C3 State 91
- 4.2.4.4 Core C6 State 91
- 4.2.4.5 Delayed Deep C-States 91
- 4.2.5.1 Package C0 93
- 4.2.5.2 Package C1/C1E 93
- 4.2.5.3 Package C2 State 94
- 4.2.5.4 Package C3 State 94
- 4.2.5.5 Package C6 State 94
- 4.2.7 Processor P 95
- Power Specifications 95
- 4.3.1 CKE Power-Down 96
- 4.3.2 Self Refresh 96
- 4.3.2.1 Self Refresh Entry 97
- 4.3.2.2 Self Refresh Exit 97
- 4.3.2.3 DLL and PLL Shutdown 97
- 5 Thermal Management 98
- 5.1.5 Thermal Metrology 107
- ) Measurement Location 108
- 5.2.1 Processor Temperature 109
- 5.2.2.2 Clock Modulation 111
- 5.2.4 PROCHOT_N Signal 112
- 5.2.5 THERMTRIP_N Signal 112
- 6 Signal Descriptions 115
- 6.5 PECI Signal 118
- 6.7 JTAG and TAP Signals 119
- Miscellaneous Signals 119
- 7 Electrical Specifications 124
- BCLK{0/1}_DN) 125
- 7.1.6.1 PLL Power Supply 126
- 7.1.9.2 Decoupling Guidelines 127
- Electrical Specifications 128
- 7.2 Signal Group Summary 132
- 7.5 Mixing Processors 136
- 7.8 DC Specifications 138
- Figure 7-3. V 142
- 7.8.2 Die Voltage Validation 143
- Time [us] 144
- Unit Figure Notes 146
- O_ABS_MAX 149
- VHavg (mV) 150
- 250 + 0.5 (VHavg - 700) 150
- 550 + 0.5 (VHavg - 700) 150
- 7.9 Signal Quality 152
- 7.9.5.3 Activity Factor 154
- 1.3335 V 0.2835 V 3 ns 5 ns 155
- 1.2600 V 0.210 V 5 ns 5 ns 155
- 8 Processor Land Listing 157
- 8.2 Listing by Land Number 175
- 9 Package Mechanical 194
- Intel® Xeon® Processor E5 195
- 9.7 Processor Materials 199
- 9.8 Processor Markings 199
- 10.1 Introduction 200
- Solution) 201
- Keepout Zones 203
- Support (URS) 212
- °C. Meeting the processor’s 213
- 10.4 Boxed Processor Contents 216
© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.035 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji