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Intel® Xeon® Processor E5-2400 v2 Product Family 185
Datasheet Volume One
Processor Land Listing
BA28 VCC PWR
BA29 PE3D_RX_DN[15] PCIEX3 I
BA3 VSS GND
BA30 VTTD PWR
BA31 PE3D_RX_DN[13] PCIEX3 I
BA32 VSS GND
BA38 RSVD
BA39 PE1B_RX_DN[5] PCIEX3 I
BA4 QPI1_DTX_DN[13] Intel QPI O
BA40 VSS GND
BA5 QPI1_DTX_DP[13] Intel QPI O
BA6 RSVD
BA7 QPI1_DTX_DP[11] Intel QPI O
BA8 VSS GND
BA9 QPI1_CLKTX_DP Intel QPI O
C10 VSS GND
C11 DDR3_CS_N[6] SSTL O
C12 DDR3_ODT[1] SSTL O
C13 DDR3_ODT[3] SSTL O
C14 DDR3_ODT[2] SSTL O
C15 VSS GND
C16 DDR3_WE_N SSTL O
C17 DDR3_MA[00] SSTL O
C18 DDR3_MA_PAR SSTL O
C19 DDR3_CLK_DP[0] SSTL O
C2 VSS GND
C20 DDR3_CLK_DP[3] SSTL O
C21 DDR3_CLK_DN[3] SSTL O
C22 DDR3_MA[03] SSTL O
C23 DDR3_MA[06] SSTL O
C24 DDR3_MA[05] SSTL O
C25 VSS GND
C26 DDR3_MA[14] SSTL O
C27 DDR3_BA[2] SSTL O
C28 DDR3_CKE[3] SSTL O
C29 DDR_RESET_C23_N CMOS_1.5
V
O
C3 DDR3_DQ[44] SSTL I/O
C30 VSS GND
Table 8-2. Land Number (Sheet 21 of 37)
Land
Number
Land Name
Buffer
Type
Direction
C31 VSS GND
C32 VSS GND
C33 DDR3_ECC[1] SSTL I/O
C34 DDR3_ECC[0] SSTL I/O
C35 DDR3_ECC[4] SSTL I/O
C36 VSS GND
C37 DDR2_DQ[26] SSTL I/O
C38 DDR2_DQS_DN[03] SSTL I/O
C39 DDR2_DQ[25] SSTL I/O
C4 TEST1 O
C40 VSS GND
C41 DDR3_DQ[26] SSTL I/O
C42 DDR3_DQ[30] SSTL I/O
C43 VSS GND
C5 VSS GND
C6 VSS GND
C7 VSS GND
C8 VSS GND
C9 VSS GND
D1 VSS GND
D10 DDR2_DQ[36] SSTL I/O
D11 DDR3_CS_N[3] SSTL O
D12 DDR3_CS_N[7] SSTL O
D13 VSS GND
D14 DDR3_MA[13] SSTL O
D15 DDR3_ODT[0] SSTL O
D16 DDR3_CS_N[0] SSTL O
D17 DDR3_BA[1] SSTL O
D18 VSS GND
D19 DDR2_MA[00] SSTL O
D2 DDR3_DQ[41] SSTL I/O
D20 VSS GND
D21 DDR3_MA[01] SSTL O
D22 DDR3_MA[02] SSTL O
D23 DDR3_MA[04] SSTL O
D24 DDR2_MA[08] SSTL O
D25 DDR3_MA[07] SSTL O
D26 DDR2_MA[14] SSTL O
Table 8-2. Land Number (Sheet 22 of 37)
Land
Number
Land Name
Buffer
Type
Direction
- Product Family 1
- Table of Contents 3
- Datasheet Volume One 10
- Revision History 11
- 1 Overview 13
- 1.1.2 Supported Technologies 14
- 1.2 Interfaces 15
- 1.2.2 PCI Express* 16
- Transaction 17
- Overview 18
- 1.3 Power Management Support 19
- 1.5 Package Summary 20
- 1.6 Terminology 20
- 1.7 Related Documents 22
- 1.9 State of Data 23
- 2 Interfaces 24
- 2.2 PCI Express* Interface 25
- 2.2.1.1 Transaction Layer 26
- 2.2.1.2 Data Link Layer 26
- 2.2.1.3 Physical Layer 26
- 2.3.1 DMI2 Error Flow 27
- 2.3.3 DMI2 Link Down 27
- Interfaces 28
- 2.5.1.1 Thermal Management 30
- 2.5.2.1 Ping() 30
- 2.5.2.2 GetDIB() 31
- Reserved 32
- # of Domains 32
- Byte# 5 32
- 2.5.2.3 GetTemp() 33
- 2.5.2.4 RdPkgConfig() 34
- 2.5.2.5 WrPkgConfig() 35
- DRAM Power Limit Performance 45
- CPU ID Data 48
- CPU code patch revision 49
- Current Config Limit Data 54
- RESERVED 54
- Accumulated Energy Status 55
- Accumulated CPU Energy 55
- Accumulated CPU Throttle Time 57
- 2.5.2.7 RdIAMSR() 59
- Cores 0,1.2...7 60
- Thread (0,1) Mask for Core4 60
- 2.5.2.8 RdPCIConfig() 63
- 2.5.2.9 RdPCIConfigLocal() 64
- DeviceBus Function Register 65
- 2.5.2.10 WrPCIConfigLocal() 66
- 2.5.3.1 Power-up Sequencing 68
- 2.5.3.2 Device Discovery 69
- 2.5.3.3 Client Addressing 69
- 2.5.3.4 C-states 70
- 2.5.3.5 S-states 71
- 2.5.3.6 Processor Reset 71
- 2.5.4 Multi-Domain Commands 73
- 2.5.5.1 Abort FCS 74
- 2.5.5.2 Completion Codes 74
- 2.5.7.1 Format 75
- 3 Technologies 77
- 3.1.2 Intel® VT-x Features 78
- 3.1.3 Intel® VT-d Objectives 78
- 3.2 Security Technologies 79
- 3.2.3 AES Instructions 80
- 3.3 Intel® Secure Key 81
- 3.4 Intel® OS Guard 81
- Technologies 82
- 4 Power Management 85
- Table 4-6. Intel® QPI States 87
- 4.2.2 Low-Power Idle States 88
- Processor Package State 89
- Core N State 89
- Core 0 State 89
- 4.2.4.1 Core C0 State 90
- 4.2.4.2 Core C1/C1E State 90
- 4.2.4.3 Core C3 State 91
- 4.2.4.4 Core C6 State 91
- 4.2.4.5 Delayed Deep C-States 91
- 4.2.5.1 Package C0 93
- 4.2.5.2 Package C1/C1E 93
- 4.2.5.3 Package C2 State 94
- 4.2.5.4 Package C3 State 94
- 4.2.5.5 Package C6 State 94
- 4.2.7 Processor P 95
- Power Specifications 95
- 4.3.1 CKE Power-Down 96
- 4.3.2 Self Refresh 96
- 4.3.2.1 Self Refresh Entry 97
- 4.3.2.2 Self Refresh Exit 97
- 4.3.2.3 DLL and PLL Shutdown 97
- 5 Thermal Management 98
- 5.1.5 Thermal Metrology 107
- ) Measurement Location 108
- 5.2.1 Processor Temperature 109
- 5.2.2.2 Clock Modulation 111
- 5.2.4 PROCHOT_N Signal 112
- 5.2.5 THERMTRIP_N Signal 112
- 6 Signal Descriptions 115
- 6.5 PECI Signal 118
- 6.7 JTAG and TAP Signals 119
- Miscellaneous Signals 119
- 7 Electrical Specifications 124
- BCLK{0/1}_DN) 125
- 7.1.6.1 PLL Power Supply 126
- 7.1.9.2 Decoupling Guidelines 127
- Electrical Specifications 128
- 7.2 Signal Group Summary 132
- 7.5 Mixing Processors 136
- 7.8 DC Specifications 138
- Figure 7-3. V 142
- 7.8.2 Die Voltage Validation 143
- Time [us] 144
- Unit Figure Notes 146
- O_ABS_MAX 149
- VHavg (mV) 150
- 250 + 0.5 (VHavg - 700) 150
- 550 + 0.5 (VHavg - 700) 150
- 7.9 Signal Quality 152
- 7.9.5.3 Activity Factor 154
- 1.3335 V 0.2835 V 3 ns 5 ns 155
- 1.2600 V 0.210 V 5 ns 5 ns 155
- 8 Processor Land Listing 157
- 8.2 Listing by Land Number 175
- 9 Package Mechanical 194
- Intel® Xeon® Processor E5 195
- 9.7 Processor Materials 199
- 9.8 Processor Markings 199
- 10.1 Introduction 200
- Solution) 201
- Keepout Zones 203
- Support (URS) 212
- °C. Meeting the processor’s 213
- 10.4 Boxed Processor Contents 216
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