NEC PD17062 Instrukcja Użytkownika Pobierz pdf (Strona 232)

232

PD17062

PLLR

0000 0110 1100 1111

06 CF

PLRFMODE

0010

6.25 kHz

18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER

The following data is necessary to control the PLL frequency synthesizer.

(1) Reference frequency : fr

(2) Division value : N

The following paragraphs explain how to set the PLL data.

(1) Setting reference frequency f

The reference frequency is specified according to the PLL reference mode select register.

(2) Calculating division value N

The division value N is calculated as follows:

N =

UCO

P × fr

where fUCO : Frequency input to the VCO pin

r : Reference frequency

P : Prescaler frequency division ratio

(3) Example of setting the PLL data

The following example shows how to specify the data required to receive channel 02 of the West Europe

TV system, assuming that the prescaler used here is the

PB595 and that the frequency division ratio P

is 8.

Receive frequency : 48.25 MHz

Reference frequency : 6.25 kHz

Intermediate frequency : 38.9 MHz

The division value N is calculated as follows:

N =

UCO

48250 + 38900

= 1743 (decimal)

P × f

r 8 × 6.25

= 06CFH (hexadecimal)

The PLL data register (PLLR, at address 41H) and PLL reference mode select register (PLRFMOD, at address

13H) are set with data as shown below.

1 2 ... 227 228 229 230 231 232 233 234 235 236 237 ... 295 296

Brak uwag

NEC PD17062 Instrukcja Użytkownika Strona 232